Chetan Parikh | International Institute of Information Technology, Banglore

Chetan Parikh

Professor

Email: chetan.parikh@iiitb.ac.in

Education

  • Ph.D. (University of Florida)

Chetan Parikh obtained his BTech from IIT-Bombay, and MS and PhD from the University of Florida, Gainesville, all in Electrical Engineering. Prior to joining IIIT-B, he has been a faculty member at IIT-Bombay, DAIICT-Gandhinagar, and the Institute of Engineering & Technology at Ahmedabad University. He was also a Visiting Faculty at Purdue University and the University of Missouri, and worked at Motorola/Freescale, Austin, Texas. His current interests are in analog and mixed-signal circuit design, innovative pedagogies for engineering education, teaching ethics to college students and and participating in setting up world-class educational institutions.

Since July, 2015, he is a Professor at IIIT-Bangalore. Currently, he also serves as a Consulting Dean to IIIT-Dharwad, and as Coordinator of the Mentoring Cell at IIIT-B for the Myanmar Institute of Information Technology at Mandalay.

Research Interests

  • Analog and mixed-signal circuit design., Innovative pedagogies for engineering education., Teaching ethics to college students.

Selected Publications

Book

J. Millman, C. Halkias and C.D. Parikh, Integrated Electronics: Analog and Digital Circuits and Systems, 2nd edition, Tata McGraw-Hill, New Delhi, 2010.

Refereed Journal Papers (the significant ones)

  1. C.D.Parikh and J. Vasi, "Modelling of a depletion-mode MOSFET," Soild-state Electronics, vol. 30, p. 699, 1987.

  2. C.D. Parikh and F.A. Lindholm, "A new charge-control model for single and double heterojunction bipolar transistors," IEEE Trans. Electron Devices, vol. 39, p. 1303, 1992.

  3. C.D. Parikh and F.A. Lindholm, "Space charge region recombination in heterojunction bipolar transistors," IEEE Trans. Electron Devices, vol.39, p. 2197,1992.

  4. C. D. Parikh and R. M. Patrikar, “A compact model for the n-well resistor,” Solid-State Electronics, vol. 43, 683, 1999.

  5. S. Mahapatra, C. D. Parikh and J. Vasi, “A new mutlifrequency charge pumping technique to profile hot-carrier induced interface-state density in nMOSFETs,”  IEEE Trans. Electron Devices, vol. 46, p. 960, 1999.

  6.  S. Mahapatra, C. D. Parikh, V. Ramgopal Rao, C. R. Vishwanathan  and J. Vasi, "A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique," IEEE Trans. on Electron Devices, vol. 47, p. 171, Jan. 2000.

  7. S. Mahapatra, C. D. Parikh, V. Ramgopal Rao, C. R. Vishwanathan and J. Vasi, "Device scaling effects on hot-carrier induced interface and oxide trapped charge distributions in MOSFETs," IEEE Trans. Electron Devices, vol. 47, p. 789, April, 2000.

  8. B. J. Daniel, C. D. Parikh, and M. B. Patil, "Modeling the CoolMOS transistor – Part I: Device physics," IEEE Trans. Electron Devices, vol. 49, p. 916, 2002.

  9. B. J. Daniel, C. D. Parikh, and M. B. Patil, "Modeling the CoolMOS transistor – Part II: DC model and parameter extraction," IEEE Trans. Electron Devices, vol. 49, p. 923, 2002.

  10. P.G. Darji, M. Upraity, C.D. Parikh, “A novel architecture for current-steering digital-to-analog converters,” UACEE International Journal of Advances in Electronics Engineering, vol. 2, pp. 38-41, 2012.

  11. P.G. Darji and C.D. Parikh, “A Novel Analog Calibration Technique for Current-Steering DACs,” Circuits, Systems and Signal Processing, vol. 34, no. 8, pp. 2407-2418, 2015. (DOI: 10.1007/s00034-015-9979-6).

  12. Purushothaman A. and C.D. Parikh, “A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators,” Circuits, Systems and Signal Processing, 2015, DOI: 10.1007/s00034-015-9988-5.

Selected Conference Papers

  1. Y. Sailaja and C. D. Parikh, "A large-signal non-quasi-static model for short-channel MOSFETs,” IXth International Workshop on the Physics of Semiconductor Devices, 1997, New Delhi.

  2. P. N. Kondekar, C. D. Parikh and M. B. Patil, “Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOSTM using theory of novel voltage sustaining layer,” IEEE 33rd Annual Power Electronics Specialists Conference, 2002, Volume 4,  23-27 June 2002, pp. 1769 – 1775.

  3. C. D. Parikh and M. S. Lundstrom, "Electron transport in nanoscale bipolar transistors," Proc. 2nd IEEE Conference on Nanotechnology, Washington, DC, Aug. 2002, p. 103.

  4.  Steimle, R.F., Rao, R., Sadd, M., Swift, C., Hradsky, B., Straub, S., Merchant, T., Stoker, M., Parikh, C., Anderson, S., Rossow, M., Yater, J., Acred, B., Harber, K., Prinz, E., White, B.E., Jr., Muralidhar, R., “Silicon nanocrystals: from Coulomb blockade to memory arrays,” Proc. 4th IEEE Conference on Nanotechnology, Aug. 2004, p. 290.

  5.  Narayana Rao, and Chetan Parikh, “Low-power high slew-rate adaptive biasing circuit for CMOS amplifiers,” in Proceedings of 11th IEEE VLSI Design and Test Symposium, VDAT 2007, Kolkata, Aug. 8-11, 2007, pp. 114-119.

  6. Anuradha Ray, and Chetan Parikh, “A2.4 GHz low-voltage CMOS low noise amplifier with 32 dB gain,” in Proceedings of 11th IEEE VLSI Design and Test Symposium, VDAT 2007, Kolkata, Aug. 8-11, 2007, pp. 100-104.

  7. Shagun Bajoria, Vineet Kumar Singh, Raju Kunde and Chetan D. Parikh, “Low Power High Bandwidth Amplifier with RC Miller and Gain Enhanced Feedforward Compensation,” International Symposium on Low Power Electronics and Design, ISLPED-2008, Bangalore, August, 2008.

  8. K. Purushothaman and Chetan D. Parikh, “Design of static latch-based comparators using power constrained optimization,” in Proceedings of 14th IEEE VLSI Design and Test Symposium, VDAT 2010, Chandigarh, July, 2010.

  9. Chetan D. Parikh, Amara Amara and D. Nagchoudhuri, “A 0.7-V rail-to-rail amplifier with double-gate MOSFETs,” 10th Low-voltage low-power (FTFC) conference – 2011, Marrakech, Morocco, June, 2011.

  10. K.A.Shaik, Amara Amara, Chetan D. Parikh and A. Singhal, “Low power and fast adder implementation with Double Gate MOSFETs,” 10th Low-voltage low-power (FTFC) conference – 2011, Marrakech, Morocco, June, 2011. 

  11. Chetan D. Parikh and Amara Amara, “A 110-MHz rail-to-rail amplifier with double-gate MOSFETs,” in Proceedings of 15th IEEE VLSI Design and Test Symposium, VDAT 2011, Pune, July, 2011.

  12. Bhavi M. Panchal and Chetan D. Parikh, “A 1.8 V Piecewise-Linear Curvature-Corrected CMOS Bandgap Reference,” in Proceedings of National Conference on Recent Advances in Electronics, New Delhi, Jan. 2013.

  13. Uday Kumar and Chetan D. Parikh, “A 1.5 V, 2.4 GHz High Performance CMOS Down-Conversion Mixer,” in Proceedings of National Conference on Recent Advances in Electronics, New Delhi, Jan. 2013.

  14. Akhil Rathore and Chetan D. Parikh, “10 Gbps Current Mode Logic I/O Buffer,” 17th International Symposium on VLSI Design and Test, Jaipur, 27-30 July, 2013.

  15. Vivek Verma and Chetan D. Parikh, “A low-power wideband high dynamic range single-stage variable gain amplifier” 17th International Symposium on VLSI Design and Test, Jaipur, 27-30 July, 2013.

  16. Venkata R. Bhumireddy, Khaja A. Shaik, Amara Amara, Chetan D. Parikh, Dipankar Nagchoudhuri, Subhajit Sen, “Design of Low Power and High Speed Comparator with sub-32-nm Double Gate-MOSFETs,” IEEE International Conference on Circuits and Systems – ICCAS 2013, Kuala Lampur, Malaysia, Sept. 2013.

Teaching


Research & Consulting


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